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Title: Novel architectures for miniaturised low-power convolutional decoders using current-mode analogue circuit techniques
Author: Demosthenous, Andreas Christodoulou
Awarding Body: University of London
Current Institution: University College London (University of London)
Date of Award: 1998
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Convolutional decoders have long been important in applications where very noisy channels are encountered, such as satellite communications. The technique has recently become much more significant with the advent of new application areas such as mobile radio systems of various types and digital magnetic disk recording. Convolutional decoders usually employ the Viterbi algorithm (VA), implemented in software or digital hardware, depending on the requirements and constraints of the application, in an attempt to reduce the power dissipation and size of Viterbi decoders, without sacrificing speed, analogue circuits have recently been employed for the realisation of certain sections of these systems. Such hybrid analogue/digital Viterbi decoders are found in today's state-of-the-art computer disk drives. However, most of the analogue Viterbi realisations reported so far employ a simplified form of the VA, and hence are not suitable for decoding convolutional codes. This thesis describes the application of the analogue current-mode approach to the design of convolutional decoders, employing both the VA in standard hybrid analogue/digital architectures, and in addition, a new convolutional decoding algorithm, which is called the modified feedback decoding algorithm (MFDA). The MFDA enables a convolutional decoder to be constructed almost entirely from analogue components, with only negligible loss of coding gain compared to a Viterbi decoder, thus offering the potential for construction of very small and economical systems. The use of analogue current-mode techniques in this application offers a more attractive trade-off in terms of speed, size and power dissipation than the conventional use of analogue voltage-mode techniques, as well as allowing operation at 2.8V or less. Furthermore, stemming from the work on decoding, this thesis also describes the design, implementation and evaluation of a CMOS winner-take-all network (WTA) which is well suited to applications requiring large WTA systems where operating speed and resolution are important parameters [e.g., vector quantisation (VQ)].
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available