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Title: Achieving power efficiency in hardware circuits with symbolic discrete control
Author: Özbaltan, Mete
ISNI:       0000 0004 8506 4520
Awarding Body: University of Liverpool
Current Institution: University of Liverpool
Date of Award: 2020
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The power efficiency of hardware circuits is of paramount importance for constructing embedded electronic devices, as it is one of the major design constraints in today's embedded systems, limiting performance, battery life, etc. This thesis targets the power efficiency in hardware circuits with symbolic discrete control. In the research proposed in this thesis, we consider hardware circuits, described using the popular Hardware-DescriptionLanguage (HDL), Verilog, at the Register-transfer Level (RTL) abstraction, as hierarchical compositions of sub-circuits. We achieve power-efficiency by switching-off the clock of each sub-circuit according to some clock-gating logic, where the technique applied is known as RTL clock-gating, which is one of the best low-power technique applied on synchronous hardware circuits. We advance the following approaches in order to produce a clock-gating logic: to switchoff the clock signal of a sub-circuit in the idle status, which is a set of values of the circuit signals when the values of the memory components do not change; to apply power-aware scheduling policies for data-flow hardware circuits implemented as Kahn-Process-Networks (KPNs), using the clock-gating logic as used to selectively filter the clocks of the sub-circuits involved; and to employ an energy-efficient configuration manager for choosing the optimal configuration, by means of the clock-gating logic, among the alternatives on data-flow hardware circuits implemented as KPN, with parallel synchronous processes. We devise a tool-supported framework for achieving power-efficiency of hardware circuits for each approach. Our approaches rely on formal control techniques, where the goal is to compute a strategy that can be used to drive a given model so that it satisfies a set of control objectives. More specifically, we give an algorithm that derives abstract behavioral models directly in a symbolic form from original designs, and for formulating suitable constraints and objectives. We encode the computation of the latter as several small symbolic Discrete-ControllerSynthesis (DCS) problems, and use the resulting controllers to derive power-efficient versions from original circuit designs. Finally, we show how a resulting strategy can be translated into a piece of synchronous circuit that, when paired with the original design, ensures the aforementioned objectives. We detail and illustrate our approaches using various hardware designs and objectives, and validate them experimentally by deriving a low-power version of the original hardware designs.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral