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Title: Dynamic CPU ISA customizations through FPGA interlays
Author: Garcia Ordaz, Jose
ISNI:       0000 0004 8504 1599
Awarding Body: University of Manchester
Current Institution: University of Manchester
Date of Award: 2018
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General purpose processors (GPPs) are designed to provide a substantial level of performance for a wide range of applications. However, GPPs, in particular those aimed to power mobile systems, face a design dilemma in which, on the one hand, they are required to deliver high performance for some applications and, on the other hand, they are required to operate very efficiently to keep energy consumption at a minimum because they are often bounded by strict energy budgets. A common approach to provide GPPs with enhanced performance is to integrate hardened instruction set extensions (ISE) as they provide application domain-specific functionality to accelerate, for example, media applications. While the hardened ISE approach can boost CPU performance, it also introduces an overhead in terms of area (and consequently, in terms of associated energy consumption). In consequence, adding more and more hardened ISEs is not well suited for battery-operated processors. Therefore, alternative approaches to tackle the previously described design dilemma for GPPs are required. To address that design dilemma, this thesis proposes embedding a small mixed-grained (FPGA) reconfigurable fabric into an otherwise hardened CPU in order to allow for a dynamic customization of a CPU ISA. In this thesis, the term “Interlay” is used to refer to this reconfigurable fabric as it logically sits between the software layer and the physical substrate of a CPU. This thesis demonstrates that an Interlay can make it possible to customize the ISA of a CPU at run-time by integrating application-specific instructions. To evaluate the feasibility of this approach, this thesis presents a case study that demonstrates that the Interlay approach is realistic and that it can provide hardened CPUs with a level of flexibility and efficiency that is not found in conventional processors. Moreover, this thesis discusses architectural and management details for the Interlay. This includes a study of the Interlay in the context of multi-processor systems. Furthermore, this thesis demonstrates different paths to generate custom instructions targeting the Interlay and presents encouraging results that show the potential performance boosts that this approach can deliver. Ultimately, with the methods, techniques, and results presented, this thesis aims to stimulate research that eventually fully exploits the potential behind the herein proposed Interlay approach.
Supervisor: Garside, James ; Koch, Dirk Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: FPGA ; Partial Reconfigution ; SIMD ; Soft-processor