Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.788971
Title: Dynamic memory management for reconfigurable hardware
Author: Xue, Zeping
ISNI:       0000 0004 8499 4742
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2019
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Abstract:
The main motivation for dynamic memory management is to increase the memory efficiency of a system by allowing memory chunks to be re-used at run-time. At a software level, programming languages such as C employ malloc() and free() functions that can be called as an application runs in order to acquire memory chunks of a requested size and return memory blocks holding objects that are no longer useful respectively. Despite the fact that software-based memory management has been studied for decades, hardware-based dynamic memory management has largely remained unexplored. With an increasing trend towards the use of hardware accelerators in both embedded and cloud applications, field-programmable gate arrays (FPGAs) are becoming widely adopted by both academia and industry. As chip densities increase, FPGAs are becoming more resource-rich. This gives the chance of mapping larger scale applications on FPGAs. For memory-demanding and memory-footprint-complex applications, the memory resource can rapidly become a constraint to designs; additionally, FPGA development flows conventionally use design-time static memory allocations. As a result, for memory footprint complex applications, the development process can be labour intensive and relies on human-engineered memory allocation. This thesis aims to find hardware solutions for dynamic memory management so that FPGA applications can use memory dynamically at run-time. The novel contributions of this thesis are: 1) A design of a hardware dynamic memory manager, SysAlloc, which is flexible in managing any range of memory size and scalable in serving an arbitrary number of clients while keeping the resource utilisation low. 2) A framework, SynADT, for implementing dynamic data structures in HLS using run-time dynamic memory management. 3) A benchmarking methodology, BenchADT, for comparing and evaluating dynamic memory managers and platforms. 4) An enhanced hardware dynamic memory manager, ZepAlloc, which, similarly to SysAlloc, can manage any range of memory size and provide memory management to any number of clients connected to the same bus, but also hides the memory-management latency to clients by using size-segregated pre-allocation queues.
Supervisor: Thomas, David Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.788971  DOI:
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