Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.786702
Title: Ultra-low-power sequential circuit design for near-threshold voltage system
Author: Cai, Yunpeng
ISNI:       0000 0004 7972 1432
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2019
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Abstract:
Near-Threshold Voltage (NTV) techniques have been demonstrated to reduce energy consumption significantly by decreasing the supply voltage approaching the threshold voltage while maintaining the scaling characteristics of Super-Threshold operation. The primary challenge in applications of NTV operation is to ensure robustness, tolerance against variability and resilience against error issues at low voltage. This research focuses on addressing the design challenges in sequential logic at NTV by providing various novel circuits, for improving the SoA designs regarding power, area, robustness, and reliability at NTV. The first contribution of this thesis is the analysis of prominent types of state-of-the-art Single-Phase Clocked (SPC) FFs and analyses their suitability for NTV operation from transistor level to system level. The yield and the design limitation issue in previously published design, TCFF, is highlighted and addressed by proposing a new circuit topology, named TCFF-NTV. The proposed TCFF-NTV improved the yield of the original TCFF by 95% and 65% power reduction compared to TCFF-based design in system level. The second contribution of the thesis is proposing the 18TSPC, a new topology of fully-static contention-free Single-Phase Clocked (SPC) Flip-Flop (FF) with only 18 transistors, the lowest number reported for this type. It achieves 20% cell area reduction compared to the conventional TGFF. Chip experimental measurements at 0.6V, 25◦C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage. Besides the 18TSPC, 3 more ULP SPC FFs are proposed based on the 18TSPC for providing various solutions for designers to target different ULP design requirements at NTV. The third thesis is the development of a novel Single Event Upset(SEU)-resilient Double Master-Latch Transmission Gate FF (DMTGFF), which is capable of self-detection and self-correction of circuit-level SEU errors. And it can operate in SEU error-free with 0.5V supply voltage (NTV level). The result shows that, compared to the widely used Triple Modular Redundant (TMR) technique, the proposed DMTGFF achieves 15% performance improvement and 25% power reduction.
Supervisor: Kazmierski, Tomasz Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.786702  DOI: Not available
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