Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.781848
Title: Interfaces and junctions in nanoscale ZnO and InAs transistor structures
Author: Mohamed, Alnazer
ISNI:       0000 0004 7967 463X
Awarding Body: Swansea University
Current Institution: Swansea University
Date of Award: 2019
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Abstract:
In this thesis, a multi-scale simulation study of Ni/InAs nano-scale contact aimed for the sub-14 nm technology is carried out to understand material and transport properties at a metal-semiconductor interface. The deposited Ni metal contact on an 11 nm thick InAs channel forms an 8.5 nm thick InAs leaving a 2.5 nm thick InAs channel on a p-type doped (1×1016 cm−3) AlAs0.47Sb0.53 buffer. The density functional theory (DFT) calculations reveal a band gap narrowing in the InAs at the metal-semiconductor interface. The one-dimensional (1D) self-consistent Poisson-Schr¨odinger transport simulations using real-space material parameters extracted from the DFT calculations at the metal-semiconductor interface, exhibiting band gap narrowing, give a specific sheet resistance of Rsh = 90.9 Ω/sq which is in a good agreement with an experimental value of 97 Ω/sq. In this thesis, ZnO thin-film transistors (TFTs) with different channel lengths (10 µm, 5 µm, 4 µm, and 2 µm) have been characterised. The current-voltage measurements indicate n-type channel, enhancement mode TFT operation with an excellent drain current saturation. A transmission line method (TLM) is employed to extract the contact resistance, effective and channel electron mobility from current-voltage characteristics in the linear regime of transistor operation. Contact resistance and both effective and channel electron mobility exhibit a dependency on the channel length as a function of gate bias (10 V and 15 V). The extracted channel electron mobility is high as 0.782 cm2/Vs and 0.83 cm2/Vs (increase by 6 %) at gate biases of 10 V and 15 V, respectively, for the 10 µm channel length as compared to effective mobility of 0.11 cm2/Vs and 0.38 cm2/Vs, at the same respective biases. The channel mobility increases from 8.9 cm2/Vs to 19.04 cm2/Vs (increase by 115 %) when gate biases increases from 10 V and 15 V, respectively, when the channel length is scaled down to 2 µm. The increase of the electron channel mobility during the channel scaling is indicative of a reduced electron scattering due to the increase in electric field along the channel. This reduction in the carrier scattering increases electron velocity because electrons will have a longer mean-free path in the scaled thin-film channels. These values indicate a substantial increase in ZnO TFTs electron mobility as compared to previously reported values for such devices. In addition, ZnO NWs field-effect transistors (NWs-FETs) fabricated by using top-down fabrication have been studied. The top-down fabrication method starts with a thin film deposition by remote plasma enhanced ALD (PEALD). The PEALD is followed by aniso-tropically reactive ion etch (RIE) to produce ZnO NWs with different channel lengths (20 µm, 10 µm, and 2 µm). Optical and electrical characterisations are carried out to study the impact of scaling channel length (Lch) in the transistors.
Supervisor: Kalna, Karol Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.781848  DOI:
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