Use this URL to cite or link to this record in EThOS:
Title: Design and scaling of lateral super-junction multi-gate MOSFET by 3-D TCAD simulations
Author: Adenekan, Olujide A.
ISNI:       0000 0004 7967 4592
Awarding Body: Swansea University
Current Institution: Swansea University
Date of Award: 2019
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternating U-shaped n/p- SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resistance. The folded U-shaped n/p- pillar uniformly distributes the electric field in the SJ drift region. The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of different carrier transport models are carried out with different doping profiles by calibrating the drift-diffusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and specific on-resistance (Ron,sp). The effect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the fixed ratio between the pillar width and the pillar height. It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-off ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V, thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device offers a specific on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the specific on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of offering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum specific on-resistance, and excellent FoM for sub-100 V rating applications. Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Different scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping profile is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low specific on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V. Additionally, the scaled SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V, respectively. Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, specific on-resistance, and physical density for a higher integration in a CMOS architecture.
Supervisor: Kalna, Karol ; Holland, Paul M. Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral