Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.776023
Title: TEM studies of III-V MOSFETs for ultimate CMOS
Author: Longo, Paolo
Awarding Body: University of Glasgow
Current Institution: University of Glasgow
Date of Award: 2008
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Abstract:
Over the past half-century electronic industry has enormously grown changing the way people live their lives. Such growth has been driven by the miniaturisation and development of the transistors which are the main components in an integrated circuit (IC) commonly referred as a chip. Until today electronic industry has been based on the use of Si and its native oxide SiO2 in transistors. However, the performance limit of conventional Si based transistors is rapidly being approached and alternatives will soon be required. One of the proposed alternatives is GaAs. n-type GaAs has a mobility 5 times higher than Si. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al, dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current. The electrical properties of the Ga2O3/Gd[x]Ga[0.4-x]O[0.6] dielectric stack are related to the Gd concentration and the quality of the GaAs/Ga2O3 interface. Over the past years in a unique partnership several research groups from the Physics and the Electronic and Electrical engineering Department have collaboratively worked for the realisation and development of such new generation of GaAs based transistors using the technology described above. The properties of such devices depend on structures at the nanoscale which is only few atoms across. Thus the characterization using the transmission electron microscope (TEM) becomes essential. In this project TEM has been used to study several MBE grown III-V semiconductor nanostructures. In particular most of the thesis is focussed on the chemical characterisation of the GaAs/Ga2O3/GGO dielectric gate stack, mainly using electron energy loss spectroscopy (EELS) and high-resolution scanning Transmission electron microscopy (STEM) imaging. As said above the quality of such interfaces affects the properties of the whole device. Hence the results presented herein represent an important feedback for the realisation of world performance GaAs devices.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.776023  DOI: Not available
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