Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.772548
Title: Integrating logarithmic wide dynamic range CMOS image sensors
Author: Shaharom, Mus'ab B.
ISNI:       0000 0004 7960 034X
Awarding Body: University of Oxford
Current Institution: University of Oxford
Date of Award: 2018
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Abstract:
Complementary Metal Oxide Semiconductor (CMOS) image sensors are widely used in many applications such as consumer electronics, automotive and security. One of the key requirements in today's imaging applications is the ability to capture natural scenes faithfully; a feature known as wide dynamic range (WDR). Current digital image sensors have a linear response that results in saturation and loss of details. Conventional CMOS image sensors with a logarithmic response attempt to address the limited dynamic range of the linear digital image sensors by exploiting the subthreshold operation of a transistor in a pixel. This results in CMOS pixels that are able to capture light intensities of more than six decades (120 dB). However, the approach comes at the expense of high fixed pattern noise (FPN) and slow response. The work presented in this thesis describes a five all nMOS transistor (5T) pixel architecture that aims to achieve wide dynamic range. This feature is obtained using a time-varying reference voltage that is applied to one of the transistors of the pixel. The reference voltage varies in a logarithmic fashion in order to modulate the effective integration time of the pixel. This allows the pixel to avoid saturation; hence extending the dynamic range. In addition, the slope of the reference voltage that can be adjusted means the pixel response is adaptive and can be more robust towards temporal noise. To have a well-controlled pixel response, the pixel non-ideal effects such as source follower gain, body effect and subthreshold effect are characterised and included as an improved model to the reference voltage. Measurement results from fabricated chips using UMC 180 nm technology are presented and analysed. A dynamic range of 80 dB with a logarithmic response of 600 mV/decade has been achieved. This is a significant improvement in comparison to that of conventional logarithmic pixel response (60 mV/decade). An analysis of the effect of chip variations that causes FPN has been conducted and correction methods that can reduce the illumination error to less than 2% have been proposed. In addition, the first experimental study comparing different dynamic range extension methods has been performed. In the study, a method to control the response of a WDR approach using a stepped voltage that has achieved a dynamic range of up to 120 dB is also presented. The result of the study leads to a modification to the reference voltage that allows an implementation of an analogue circuit to generate the reference voltage.
Supervisor: Collins, Steve ; Choubey, Bhaskar Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.772548  DOI: Not available
Keywords: Microelectronics
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