Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.770368
Title: High performance pixels for CMOS image sensors
Author: Brunetti, Alessandro Michel
ISNI:       0000 0004 7652 2358
Awarding Body: University of Oxford
Current Institution: University of Oxford
Date of Award: 2017
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Abstract:
Complementary Metal-Oxide Semiconductor (CMOS) image sensors are the principal technology employed in commercial image sensing applications. The research interest in these devices is driven by the high demand of cameras. High-quality imagers are relevant in the mobile devices business and are even more important in the automotive market segment where the image quality is crucial for safety. However, CMOS image sensors performance can still be improved. In particular, a leakage current, intrinsic to the process of manufacturing CMOS technology, reduces the sensitivity in low light and should be minimised. In addition, the capability of the sensor to collect electrons, known as full well capacity, should be maximised. The methods proposed in the literature to reduce the leakage current and to increase the full well capacity are either insufficient or costly as they may require process modifications. To overcome these limitations, a different approach based on simple layout modifications is proposed. The principal source of leakage current is due to the photodiode isolation. By designing pixels adjacently, the isolation can be removed thereby reducing the leakage current contribution. In order to maximise the full well capacity, a novel technique is proposed here which consist in minimising the area reserved to the transistors in the pixel array by sharing the maximum number of diffusions. The result is a pixel with a 50% increase in fill factor compared to a traditional pixel. The proposed optimisation strategy results in a staggered pixel arrangement. This may introduce artefacts in the image when displayed. Hardware-efficient image reconstruction algorithms able to correct the artefacts are presented. Test chips were manufactured to prove the performance improvement and experimental data showed that the proposed layouts effectively reduces the leakage current and improved the full well capacity of the presented pixels. In addition, the proposed algorithms are shown to correctly reconstruct and represent the staggered acquired image on a standard display.
Supervisor: Choubey, Bhaskar Sponsor: EDISON Marie curie EID ITN FP7
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.770368  DOI: Not available
Keywords: CMOS image sensor ; Analogue Design ; Pixel
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