Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.761128
Title: Exploring hardware support for resource management in the data centre
Author: Chen, Qianqiao
ISNI:       0000 0004 7432 7890
Awarding Body: University of Bristol
Current Institution: University of Bristol
Date of Award: 2018
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Abstract:
The management of data centre resources has become important as their size, complexity, and power consumption are increasing. Efficient resource utilisation helps reduce the construction and maintenance costs of data centres. Using that background as a starting point, this thesis explores hardware support that increases the efficiency of resources in data centres. Either optimising existing data centre architectures or establishing new data centre architectures has a strong requirement on the data centre network. Therefore, this thesis establishes a network interface equipped with the new OptoPHY optical transceiver. The feasibility and quality of an optical transceiver when it is combined with a server board are evaluated by comparing it with a traditional SFP+ transceiver. The reconfigurable FPGA platforms have a great potential to reduce power consumption and maintenance costs due to their high-volume programmable parallel processing features. Therefore, this thesis tries to explore the management of FPGA resources in a data centre environment. Based on partial reconfiguration technology, an architecture that would virtualise the FPGA platforms is proposed and implemented. Resources on the FPGA chip are partitioned into several regions. Furthermore, an interconnect system is implemented to share I/Os with all of the regions and enable communication between regions. When several FPGA platforms are combined for pipelined stream processing, it is difficult to perform function reconfiguration over multiple FPGA platforms that have a short downtime. That is because it is hard to predict the network delay of reconfiguration requests sent from a centralised manager. Therefore, a new network protocol is proposed, and the associated protocol processor is implemented to synchronise the reconfigurations of related FPGA platforms.
Supervisor: Nunez-Yanez, Jose Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.761128  DOI: Not available
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