Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.759245
Title: Clock generation for silicon photonics based optical communication systems
Author: Meng, Fanfan
ISNI:       0000 0004 7431 2904
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2018
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Abstract:
As communications data traffic continues to increase, electronic interconnects over short reaches are struggling to keep up with the bandwidth and power consumption requirements. One of the technology trends is to migrate from copper to optical based interconnects where silicon Photonics (SiP) technology has emerged as an excellent technical solution to meet the performance and cost requirements of these short-reach applications. The clock generation system is a critical module that none of the communication systems can overlook. However, the reported clock generation solutions utilized in SiP transceivers inherit limitations from traditional electronic interconnects, where the clock signals are limited by the frequency tuning range, system settling time and the number of clock phases. The motivation for this PhD project is to build a novel clock generation system that can be fully integrated with future SiP transceiver and the innovation has been realized in various aspects of the work. Firstly, a novel high-speed ring-based voltage-controlled oscillator (VCO) is proposed using inductor peaking. The proposed VCO topology was validated with four design examples fabricated in different CMOS processes nodes (130nm and 65nm) and measured results show close agreement with theoretical analysis. The figure of merit (FOM) of 203 is the best combination of frequency and tuning range currently. Secondly, a dedicated phase locked loop (PLL) structure combined with the inductor peaking VCO was created, focussing on the requirements of frequency controllability and system settling time for SiP communication system. A programmable frequency range of more than 25GHz has been achieved using a 40nm process while the measured phase locking time is always less than half of a microsecond. Finally, with the mainstream CMOS process for analogue circuits design migrating towards to 28nm High-k/Metal Gate (HKMG), design methodologies on the proposed VCO have been realized in order to adapt this evolution. Two specific design cases have been implemented to fully utilize the advantages of new CMOS process and mitigate the side-effects of 28nm HKMG process.
Supervisor: Reed, Graham ; Li, Ke ; Thomson, David ; Lacava, Cosimo ; Littlejohns, Callum ; Byers, James ; Mailis, Sakellaris ; Peacock, Anna ; Husain, Muhammad ; Gardes, Frederic ; Saito, Shinichi Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.759245  DOI: Not available
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