Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.758364
Title: Current limiting devices for short-circuit protection of DC systems in aerospace applications
Author: Alwash, Mahmood
ISNI:       0000 0004 7431 1370
Awarding Body: University of Sheffield
Current Institution: University of Sheffield
Date of Award: 2018
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Abstract:
The use of DC systems to power high-power loads offers many advantages over AC in terms of efficiency and flexibility. Due to the increasing demand for electric power in aircrafts, the need for wider adoption of DC-based networks has been growing. This demand for higher power has originated from various efforts to electrify aircrafts ranging from replacing some of the mechanical components of jet engines with lighter electrical alternatives up to completely replacing jet engines with electric propulsors. Most of these efforts have been experimental, and no electric or 'more-electric' aircrafts are commercially available as of the writing of this thesis. One of the main challenges hindering wider adoption of DC-based networks in aircraft systems is addressing concerns pertaining to system reliability. These concerns are emphasized by the lack of detailed analyses of possible fault scenarios and appropriate technologies for fault protection. This thesis aims to address these concerns by first presenting detailed analyses of the most severe fault scenario in AC/DC power converters, which are common components in DC-based power systems used to interface with AC networks or electric machines. Then, using the information provided by the analyses, current limiting devices are developed for fault protection. These are unique devices which take advantage of recent developments in Silicon Carbide materials that have produced Junction Field Effect Transistors (JFETs) with significantly higher performance than their Silicon counterparts. The resistance of the JFET is varied with the magnitude of current so that the circuit experiences the most amount of resistance under a fault condition and the least amount of resistance under nominal conditions. Two circuit configurations are presented one having the least complexity (maximum reliability) and one which is more complex but offers significant performance benefits.
Supervisor: Madathil, Shankar Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.758364  DOI: Not available
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