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Title: Computationally efficient adaptive spike processor with real-time decoding of neural signals for implantable applications
Author: Zamani, M.
ISNI:       0000 0004 7224 4856
Awarding Body: UCL (University College London)
Current Institution: University College London (University of London)
Date of Award: 2017
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Recent advances in the field of neuroscience have suggested that new generation brain computer interfaces demand a critical step in biomedical signal processing requiring online/on-chip spike sorting. Spike sorting is the process of grouping signals from an individual neuron by grouping action potentials (spikes) into a specific cluster based on the similarity of their shapes. The extraction of single-unit activity by sensors at a distance from specific neurons is necessary for a wide range of clinical applications such as disorder treatments, muscular stimulation (e.g., epidural spinal cord stimulation for treatment acceleration), cochlear implant and neural prostheses. A brain machine interface, for example, can potentially substitute the missing motor pathway/sensory information between the motor cortex and an artificial limb. With the aim of developing an energy-efficient spike sorting chip for hardware implantable systems, this thesis introduces a new feature extraction method based on extrema analysis (positive and negative peaks) of spike shapes and their discrete derivatives. The proposed method runs in real-time and does not require any offline training. Compared to other methods it offers a better tradeoff between accuracy and computational complexity using online sorting. It additionally eliminates multiplications which are computationally expensive, power hungry and require appreciable silicon area. A minimum power limit for implantable neural front-end interfaces is also derived. It involved: 1) system level optimization - the front-end specifications including the bandwidth, data converter resolution and sampling rate were defined by exploring the effect of the parameters on spike sorting via a standard spike bank; 2) block level optimization - The front-end power was minimized by using an opamp-less cyclic converter; and 3) estimating the power limit equation of the frontend. The new optimization methodology addresses the future demands of neural recording interfaces. Finally the thesis presents the design, implementation and testing of the first generation of an adaptive spike sorting processor. It enhances the accuracy-power characteristics by employing self-calibration of processing features. The chip prototype was fabricated in a 180-nm CMOS technology. It achieves an overall clustering accuracy of 84.5% using a standard spike data bank and has a power consumption of 148-μW from 1.8-V supply voltage. The fabricated spike processor has almost 10%higher clustering accuracy than the state-of-the-art. Measurements show good power-performance characteristics compared to the state-of-the-art online and offline clustering methods.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available