Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.742276
Title: Design, simulation and analysis of RESURF Si/SiC power LDMOSFETs
Author: Chan, Chunwa
ISNI:       0000 0004 7228 0099
Awarding Body: University of Warwick
Current Institution: University of Warwick
Date of Award: 2018
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Abstract:
It is necessary for power laterally diffused MOSFETs (LDMOSFETs) to operate efficiently and reliably in high temperature (< 300 °C), hostile environments such as those found in downhole, space, automotive and aerospace applications. Currently, silicon-oninsulator (SOI) technology is a dominant method to achieve this goal due to low leakage current and complete electrical isolation. However, the buried oxide (BOX) layer causes self-heating, which can impact device performance, cause thermal runaway and shorten device lifetime. To address this issue, one solution is to combine a silicon thin film with a semi-insulating (SI) SiC substrate, forming the Si/SiC architecture. LDMOSFETs built on this substrate are expected to deliver much better thermal performance, with electrical isolation comparable to the SOI case. However, the Si/SiC LDMOSFETs do not have a strong substrate assisted depletion effect, which can result in poorer electrical performance than those of the Reduced Surface Field (RESURF) bulk-Si and SOI LDMOSFETs. This thesis investigates the PN and SOI RESURF layouts and uses them to optimise 190 V and 600 V Si/SiC LDMOSFETs. DC and transient modelling will be conducted on the optimised Si/SiC and their SOI and bulk-Si equivalents. Based upon this, several comparative studies are conducted on their simulation results to see the effects of the Si/SiC architecture on the LDMOS designs. The comparative studies are made on the 600 V Si/SiC LDMOSFETs and their bulk Si and SOI equivalents. It is shown that the Si/SiC devices have the potential to operate with an off-state leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. A clamped-inductive switching circuit is simulated for the Philips SOI and the Si/SiC equivalent. It is shown that even though the SOI has a smaller chip area and suffered from strong substrate effects during the transient state, the two devices had similar currents and power dissipations at the gate, drain and source. The turn-on losses are higher than that of the turn-off losses due to the presence of parasitic capacitors. However, these similarities do not lead to similar thermal responses in both devices and the SOI is heated up at a much faster rate. By contrast, the SiC substrate in the Si/SiC behaves like an embedded heat sink regulating device temperature close to that of the ambient environment (423 K). In the high current condition, the peak temperature in the Si/SiC is 425 K, lower than 463 K in the SOI, thereby increasing reliability. The comparative studies are carried out on the 190 V LDMOSFETs in SOI, Si/SiC, Partial SOI (PSOI) and PSOSIC technology, based upon a capacitive and an inductive switching circuit. It is revealed that in spite of having a chip area 75% larger than the SOI structure, the Si/SiC solution undergoes negligible heating in any of the switching conditions simulated, exhibiting a very high energy capability. By contrast, the 22% area increase in the PSOSiC does not considerably change the way the energy is handled. This indicates that the Si/SiC is much more effective than PSOI and PSOSIC in dealing with the transient heating.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.742276  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering
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