Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.739898
Title: All-GaN integrated cascode configuration
Author: Jiang, Sheng
Awarding Body: University of Sheffield
Current Institution: University of Sheffield
Date of Award: 2018
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Abstract:
GaN based power device, due to its superior material properties, have attracted much attention. Remarkable progresses have been made in realising normally-off operations and improving the overall performance as power switches. GaN + Si cascode features reduced Miller-effect that improves the switching speed and hence efficiency compared to conventional Si MOSFETs. This study proposes a novel all- GaN integrated cascode combining the advantages of the GaN enhancement mode device and the cascode configuration. An all-GaN integrated cascode heterojunction field effect transistor was designed and fabricated for power switching applications. A threshold voltage of +2 V was achieved using a fluorine implant treatment and a metal-insulator-semiconductor gate structure. An output current of 300 mA/mm was optimised by matching the current drivability of the enhancement and depletion mode parts. For the first time, we demonstrate the switching speed advantage of the cascode over equivalent GaN standalone devices using double pulse tester at 200 V. A comprehensive understanding of switching behaviour of an integrated cascode is presented. Analysis shows that speed advantage originates from the reduced Millereffect leading to larger charging (discharging) current of the output capacitance. A small ratio of the gate driving current to the load current was found to enhance the advantage. However, the additional capacitance loss at the internode needs to be minimised. Field plate geometries were found to be effective in suppressing the dynamic Ron and reducing the Miller capacitance. Experimental and simulated results suggested that the cascode with a field plate connected to the source can significantly suppress the additional capacitance energy loss at the internode due to the reduced drain-source capacitance of the depletion mode device. While devices with the field plate connecting to the E-mode gate exhibit an improved switching controllability via gate resistance during turn-off.
Supervisor: Houston, Peter Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.739898  DOI: Not available
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