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Title: Network fault analysis with increased distributed generation penetration and evaluation of solutions to issues caused by distributed generation
Author: Qin, Han
ISNI:       0000 0004 7224 3140
Awarding Body: University of Warwick
Current Institution: University of Warwick
Date of Award: 2017
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Due to concerns of climate change, an increasing number of distributed generation (DG) units have been installed globally in the last two decades. This lead to issues on many aspects in the distribution network operation and management, in which the two most concerned issues are the voltage violation and fault level increase. To regulate the voltage profile and control power flow in the network, power electronic devices based soft open point (SOP) has been developed and trailed in the distribution network according to recent research. These studies mainly focused on the functions and control strategies of the power electronic compensator. However, the protection strategy and power loss of the power electronic device used in the SOP have been rarely investigated. In addition, conventional fault analysis neglects the fault current contributed from domestic load, which is hindering, and the increase DG penetration. In this work, the short-circuit behaviour of small sized induction machines in domestic load has been studied. A method for the estimation of fault current by load with higher accuracy is developed. Furthermore, the short-circuit behaviour of small and medium sized synchronous machine based DG has been investigated. A recommendation on the first symmetrical short-circuit current for synchronous machine based DG has been proposed for the situation when detailed information of the DG is unavailable. A study on the fault level change due to changes in both generation and load in the UK distribution network has been conducted and the results are presented. Regarding the SOP protection strategy, two topologies using thyristor crowbars in the protection of static synchronous series compensator (SSSC) based SOP are proposed. For these two protection topologies, the feasibility of the strategy has been thoroughly analysed in several aspects. The results indicate that with proper selection in the thyristor crowbar and coupling transformer, these protection topologies are feasible and effective. To investigate the power loss for the power electronic devices, several cases have been studied based on 11kV distribution network model with back to back voltage source converter (B2B VSC) based SOP. The results show that in most cases, the utilisation of B2B VSC based SOP can reduce the total network loss. Nevertheless, when the DG penetration level or the imbalanced loading level between two feeders is low, the B2B VSC will further increase the total network loss. Finally, one of the solutions to the fault level issue due to the DG installation is to employ fault current limiter (FCL) into the distribution network. The power loss of saturated iron core FCL has been analysed. The results show that the power loss of a saturated iron core FCL can be 1% or even less of the transferred power. It is more efficient compared to the power semiconductor type for the fault current mitigation.
Supervisor: Not available Sponsor: Western Power Distribution
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering