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Title: Fabrication and characterisation of 3C-SiC on Si semiconductor devices
Author: Li, Fan
Awarding Body: University of Warwick
Current Institution: University of Warwick
Date of Award: 2016
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Attributed to the superior electrical and thermal properties, wide band gap semiconductors have been considered as the next generation electronic materials, among which 4H-SiC is the most mature technology. Even though, currently wide band gap devices are still not widely adopted, mainly due to the much higher cost compared with conventional Si devices. Large area 3CSiC wafer grown directly on Si substrate is considered as one of the approach to make wide band gap materials more cost attractive. As such, this thesis is focused on the developments of fabricating semiconductor devices on 3C-SiC/Si materials. A degenerate wide band gap semiconductor is a rare system. In general, dopant energy levels lie deeper in the band-gap and carriers freeze-out even at room temperature. Nevertheless, we observed that heavily doped n-type degenerate 3C-SiC films are achieved by nitrogen implantation level of 6×1020 cm-3 at 20 K. Free donors are found to saturate in 3C-SiC at 7 × 1019 cm-3 and fully thermally ionized at 150 K. Ohmic contacts (Ti/Ni bilayer) were manufactured on these implanted 3C-SiC surface and the electrical characterisation revealed the unique accumulation-type metal-semiconductor interface. As-deposited Ti/Ni Ohmic contact was obtained with low contact resistivity around 2×10-5 Ω.cm2 and even lower contact resistivity approaching 1×10-6 Ω.cm2 was achieved by performing a post metallisation annealing at 1000°C for 1 min after the contact deposition. Both lateral MOS capacitors and lateral MOSFETs were fabricated on 3C-SiC(001)/Si wafers to study the 3C-SiC/SiO2 interface. Oxidation temperature above 1200°C turned out to have negligible influence on the final MOSFET peak channel mobility. O2 dry oxidised MOSFETs readily have a relatively high mobility around 70 cm2/V.s while a N2O post oxidation annealing further increases it to 90 cm2/V.s. LDMOSFETs were fabricated on 3C-SiC(001)/Si wafers. Despite of the low current density of 1.37 A/cm2, it is still more than 10 times higher than the 4H-SiC reference device. Finite element simulation demonstrated that the 3C-SiC/Si lateral device current density can be greatly increased (above 3 times) using novel RESURF structures.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering