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Title: Hafnium oxide based gate stacks on germanium and silicon
Author: Mather, Sean
ISNI:       0000 0004 6422 736X
Awarding Body: University of Liverpool
Current Institution: University of Liverpool
Date of Award: 2017
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Up until 2007 the heart of the metal-oxide-semiconductor-field-effect-transistor (MOSFET) in computer processors was based on the Si-SiO2-poly Si system. This changed when Intel announced the fabrication of the high-k metal gate MOSFET. This was required because the SiO2 layer had become too thin so that quantum mechanical tunnelling meant that the leakage current through the device was unacceptably high. As the high quality SiO2 layer was the main reason for silicon it is now possible for a semiconductor with better electrical properties to be used. The International Technology Roadmap for Semiconductors (ITRS) states that this is due to happen in 2018. Germanium is one of the contending materials due to high carrier mobilities (2x electron and 4x hole enhancement over silicon). This thesis studies the development of high-k dielectrics deposited by atomic layer deposition (ALD), specifically the dielectric constant enhancement of HfO2 with the addition of titanium. Different preparation methods were then deployed to create Hafnium based gate stacks on germanium. These methodologies are divided into 4 sections. Firstly, to grow a germanium oxide layer by oxygen plasma with the subsequent deposition of high-k on top. Then Molecular Beam Epitaxy (MBE) of an ultra-thin aluminium layer to create an ultra-thin gate stack with high-k deposited on top to reduce the leakage current through the devices. Then ALD of a thin Al2O3 layer with high-k on top and finishes with sulphur passivation of the Ge interface with high-k on top. These material systems were characterised by both physical (ellipsometry, X-ray diffraction, X-ray photoelectron spectroscopy, Transmission electron microscopy) and electrical (Capacitance-voltage, Current-voltage) means. The dielectric constant of HfO2 was found to increase from 17 to 35 for the Ti0.5Hf0.5O2 system. This then reduced upon annealing to 27 with a 30 minute N2 anneal at 500°C and 22 with a 30s spike anneal at 850oC.Growing a germanium oxide layer by oxygen plasma gave reasonable C-V characteristics but the thickness of the layer at 3nm was too large to make it suitable for extremely scaled devices. By giving the germanium a thermal clean in the MBE chamber and depositing an ultra-thin Aluminium layer which was subsequently oxidised a structure with an equivalent oxide thickness of 1.3nm were achieved with low leakage currents of 2x10-4Acm-2 and low hysteresis of 10mV. The leakage current dropped to 3x10-7Acm-2 for a sample with an EOT of 1.5nm. The equivalent oxide thickness (EOT) was found to be related to the temperature of the thermal preclean with higher temperatures giving lower EOT's due to a more efficient removal of the native oxide. EOT was also found to reduce for samples after a forming gas anneal which is attributed to densification of the layers and a reduction of the GeOx interfacial layer. ALD of a thin Al2O3 layer and subsequent plasma ALD of HfO2 showed that significant regrowth of GeOx occurs even when 2nm thick Al2O3 barrier is employed. The electrical data is similar to samples without the Al2O3 layer which could be due to it not being thick enough to suppress an unwanted interfacial layer forming. Sulphur passivation gave very good C-V data when Al2O3 is used as a dielectric and conduction band offsets were calculated as being 3.3eV for S-passivated samples and 3.61eV without S-passivation. Both of these are well over the 1eV set out by the ITRS to reduce carrier injection from the channel through the device. Device performance was found to be not as good when HfO2 was used as the dielectric as there is significant regrowth of the GeOx interfacial layer. These studies show that there are a number of possible routes available for forming a gate stack on germanium and the control of the interface is the critical performance factor that needs to be controlled.
Supervisor: Chalker, P. R. Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral