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Title: A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers
Author: Tanhaei, Ghazal
ISNI:       0000 0004 5994 6773
Awarding Body: University of Birmingham
Current Institution: University of Birmingham
Date of Award: 2016
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In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor.
Supervisor: Not available Sponsor: University of Birmingham
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: QA75 Electronic computers. Computer science ; TK Electrical engineering. Electronics Nuclear engineering