Title:
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Non-neural computing on the SpiNNaker neuromorphic computer
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Moore’s law scaling has slowed dramatically since the turn of the millennium, causing new generations of computer hardware to include more processor cores to offer more performance. Desktop computers, server machines, and even mobile phones are all multi-core devices now, and this trend has shown no signs of slowing soon. Eventually, computers will contain so many cores that they will be an abundant resource. Using this many processors requires new ways of thinking about software. Biology leads computer architecture here: mammalian brains contain billions of neurons embedded in a dense fabric of synapses—the human brain contains about 1011 neurons and 1015 synapses. Each neuron is essentially a small processing element in its own right. Neuromorphic hardware draws inspiration from this and is typically used to support neural network simulations. SpiNNaker is one such platform, designed to support simulations containing up to 109 neurons and 1012 synapses (about 1% of a human brain) in biological real-time. This is achieved by embedding a million ARM processors in a bespoke interconnection fabric which is non-deterministic, modelled after spiking neural networks, and predicated on the inherent fault-tolerance present in biological systems. This thesis uses SpiNNaker as a test-bed for massively-parallel non-neural applications, showing how very fine-grain parallel software can be structured to solve real-world problems. First, we address the inherent non-determinism of the underlying platform, by designing a set of algorithms that discover the topology of an arbitrary SpiNNaker-like machine so that fine-grain parallel software can be mapped onto it. These algorithms are verified against various fault conditions, and remove a shortcoming present in the existing system. Secondly, we demonstrate a fine-grain parallel application, by solving two-dimensional heat-diffusion where each point of the problem grid is essentially a self contained program. This software architecture is subject to various fault conditions to demonstrate the resilience of the approach.
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