MIMO strategy is a key component of modern high throughput wireless communication. Robust detection algorithms are required to retrieve the signals at receiver in MIMO systems. However, these detection algorithms are of remarkable computational complexity and pose a substantial real-time embedded computing problem. Though the real-time solutions on FPGA have enabled such systems, large scale complex architectures are required to do so, demanding detailed manual desigli of circuit architectures. This thesis solves this design problem by addressing synthesis tools for 'Iarge scale detectors on FPGA. A cooperative actor-oriented synthesis (cooperative synthesis) approach is presented, enabling real-time implementations (480 Mbps for IEEE 802.11 n) of the FSD and SSFE detectors, using massively parallel softcore processor networks. This approach has also been applied to a BSS-EFE detector, which eliminates the restrictions and computational redundancies in SSFE to enhance the robustness of algorithm. More than 1 dB SNR gains is achieved with computational complexity reduced by 16:2%. With an alternative ordering approach, complexity may be reduced by 53 :26%. Applying the cooperative synthesis approach, the only recorded realization of this algorithm for IEEE 802.11n is presented.