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Title: Low frequency noise in silicon carbide & graphene electronics
Author: Chan, Hua Khee
ISNI:       0000 0004 5370 0246
Awarding Body: University of Newcastle upon Tyne
Current Institution: University of Newcastle upon Tyne
Date of Award: 2015
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The electrical noise phenomenon in semiconductor devices has been an on-going research topic throughout the evolution of semiconductors, having been discovered in the characteristics of a vacuum tube [1]. Being a naturally occurring phenomenon, due to the microscopic interaction of conducting carriers with defects in the lattice structure, electrical noise can never be eliminated completely. Instead the degree of current/voltage fluctuations can only be reduced if the noise origin is known and well-understood. Amongst the types of electrical noise identified, the low frequency or 1/f noise is the most studied phenomenon, owing to the valuable insight that it gives in relation to the degree of crystal perfection, structural quality of fabricated devices and device reliability; as well as its impact and disturbance on circuit operation. In this thesis, the focus is on exploring the characteristics of low frequency noise on electronic devices made using silicon carbide, in particular, a high temperature signal-level junction field effect transistor (JFET), and 2D graphene film utilising an epitaxially grown graphene field effect transistor (GFET). One of the advantages of using SiC electronics is its ability to operate at higher temperatures than conventional Si and SOI technologies, where theoretical predictions of operation above 800°C and practical device operation up to 600°C have been demonstrated [2]–[5]. The realisation of high temperature devices opens up a new opportunity for functional electronic systems in hostile environment applications, such as in space exploration, geothermal/geo-exploration plus monitoring capability and thermal/nuclear reactor inspection. As one of the key design considerations in analogue circuits, the low frequency noise defines the minimal recoverable input signal of an amplifier, limits the down-scaling of signal level & transistor sizes, and affects the RF circuit operation in the form of phase noise. In the effort to facilitate the transistor optimisation process in enabling functional SiC electronics in extreme environment, the electrical noise origins of JFET with 9μm and 21μm gate length with multiple gate width dimensions were investigated. The noise behaviours of the transistor variants are each dominated by the generation-recombination (G-R) process and contribution of resistive noise components. Furthermore, the temperature dependence of the JFETs noise characteristics measured from 300K to 700K can be distinctively correlated to each JFET variants, where the trap assisted G-R mechanism and the low-field mobility-temperature dependence can be used to describe the acquired results correspondingly. Abstract v In the effort to deploy SiC electronics in extreme environment, it is imperative to first understand the electrical performance and lifetime of SiC devices, when subjected to prolonged operating conditions. This is useful to pinpoint the expected operational lifetime and ensure the reliability of these critical electronic components. Whilst, the DC and AC characteristics may offer a restricted amount of information on the level of device degradation, any abnormality in device operation can be better detected by low frequency noise measurements, where the degree of noise deviation between the good and damaged devices often exceeds those observed using DC and AC parameters. The reliability of SiC JFETs subjected to 1000 hours of high temperature stressing was examined utilising both current-voltage and low frequency noise behaviour. The degraded device structures of the stressed SiC JFETs can be successfully segregated by comparing the low frequency noise and current-voltage characteristics between the aged and as-fabricated samples. It was found that the degradation of contact metallisation governed the transistor noise properties at drain-source voltages ≤1.25V and the enhanced multi level G-R process from traps generated in the active transistor structures dominate the noise at drain-source voltages >1.25V. Graphene has gained a significant amount of research attention in recent years, owing to its superlative material properties. The ultra high carrier mobility, large surface to volume ratio, and potentially ultra low noise property, position graphene as an attractive candidate in fabricating remarkable switching devices and sensor nodes that surpass current state-of-the-art technology. Whilst, the ideal graphene characteristics may seem extraordinary, in practice the actual device properties do not match theoretical predictions, due to the material synthesis and device fabrication processes, which introduce unintentional defects into the system. The influence of gate dielectric formation is investigated by correlating noise measurements with conventional DC and AC parametric testing. The obtained noise results illustrate that the normalised current noise magnitude shows a power dependency with the channel resistance. An enhanced hysteresis effect is also observed for epitaxial GFETs that can be correlated to the quality of the graphene/oxide interface formed during gate dielectric formation. The Hall Effect mobility and noise properties of these GFETs were mapped on wafer scale (16mm×16mm) to examine the material and device reproducibility and repeatability for large scale manufacturing. The inverse relation between the GFETs low frequency noise and the Hall Effect mobility and the weak sheet resistance dependence on the sheet electron concentration, implies a short-range mobility scattering related noise origin.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available