The growth of semiconductor manufacturing technology has improved the performance of processor in an exponential level. However the high clock frequency and high density of transistors brings enormous challenges in traditional synchronous processors design, e.g. power consumption, complexity of design and verification, reliability and time to market. Asynchronous design style promises to provide low power consumption and ease of reuse by removing global clock and the use of delay-insensitive module interfaces. Through reconfigurable logic customisation, a reconfigurable computing architecture potentially achieves instruction-level parallelism by grouping and executing several instructions in the reconfigurable functional unit. And the multithreaded architecture is effective to exploit coarse-grain parallelism in thread level. We envisage a synergistic combination of these techniques will bring benefits in microprocessor architectures design. A novel architecture named MAPS+ (Micronet-based Asynchronous Processor System plus reconfigurable function units) is described in detail in this thesis, which combines hard-programmability, in the form of field programmable logic, soft-programmability in a multithreaded instruction set architecture. Compiler techniques for extracting instruction level parallelism and thread level parallelism have also been investigated in the thesis. The simulation results for a subset of the MiBench benchmarks on an event-driven instruction set simulator of the MAPS+ architecture demonstrates the performance improvement of different combination of architecture design techniques and the trade-offs of power consumption.