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Title: An investigation of CMOS sensing circuits using hexagonal lattices
Author: Purcell, M. D.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2002
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Traditionally, colour images have been captured by image sensors with a trichromatic checkerboard colour filter using the Bayer Pattern. This filter exhibits non-optimum colour aliasing. The following thesis introduces a novel way of processing an image using a hexagonal array with trichromatic or quadrochromatic filters. This form of processing ensure that all colours are equally sampled, and that the resolution in all directions for all colour channels is practically the same. This leads to a minimisation of aliasing if the lens is optimised for the array. A CMOS camera was manufactured with a standard OS process. Using raw data captured by the camera in association with colour filters, the trichromatic and quadrochromatic colour filter array options were evaluated. The implementation of the colour processor using switched capacitors is investigated alongside the more conservative digital route. A switched capacitor readout buffer is designed and simulated to test the overall performance of the circuit. Using this information, the design based on a switched capacitor implementation for the colour processor is evaluated and rejected. The digital resources required by the new system are investigated by programming an FPGA capable of processing raw data from the hexagonal CMOS camera into a colour picture in real-time. The resulting digital resources required to reconstruct an image from a camera with hexagonal pixels is compared to those needed by the Bayer pattern. Finally since the processing of the image is going to be performed on the same die as the sensor, the supplies are going to be affected by the switching elements, whether the colour processor is implemented in switched capacitor or digital form. This thesis also investigates how the pixels react to varying supplies, and how to render them more resistant to variations in the supplies, so as to deliver a better picture at a minimum cost. Various solutions to improve the power supply rejection of the camera are investigated and simulated. The more interesting options are laid out and tested.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available