This work investigates the performance limitations of selected CMOS sensor technologies comparing them with an interline CCD imager. The derived performances are used to evaluate whether the claimed benefits mentioned above apply now and will continue to do so over the next decade. The digital-camera and multimedia markets are widely predicted to expand rapidly within the next few years. In these markets, an essential function of an imaging system is analogue-to-digital conversion (ADC). Consequently, ADC is considered as an example of the on-chip integration of support circuitry. Analysis demonstrates the potential system-power saving of parallel focal-plane signal processing and discusses the most suitable converter architectures. A test-chip, designed to validate conclusions from the theoretical analysis, is described. Finally, the results from the test-chip are compared to the developed theory. From this work, conclusions are drawn as to the viability and future development of CMOS imagers; specifically, applications are highlighted where the CMOS imager is most likely to be preferable to the CCD sensor. A number of suggestions for future research are made throughout this work.