New communication standards and the requirements of modern mobile-device’s users push silicon towards processing more data in an increasingly shorter time; this is accurately the case for new compression formats targeting high-quality low-bandwidth multimedia. This presses forward the need for new programmable hardware solutions that intrinsically achieves generality, high-performance and, most importantly, low power consumption. This work investigates the design of reconfigurable hardware architectures to address these issues. Two novel solutions are thus proposed along with the implementation of several multimedia applications on them; the first architecture fits as a middle ground between FPGAs and ASICs in terms for performance and costs. This is achieved by using coarse-grain functional units combined with programmable interconnects to build flexible, high-performance and low-power circuits. A framework for generating and programming the custom domain-specific reconfigurable arrays is also proposed. The tool-flow leverages some of the design effort that goes in creating and using the arrays by facilitating the reuse of previous design elements. Furthermore, this work proposes novel direction-aware routing elements to allow efficient tailoring of interconnects structures to the application. The second proposed processing architecture adds the dimension of high-level programmability to the reconfigurable arrays. This is achieved by using functional units that can be directly matched to elements in a complier’s internal representation of software. By using a custom instruction-controller the array can execute control operations in a similar way to processors, while at the same time allowing highly efficient mapping of datapath circuits. Coupled to the low-power and high-throughput achieved, this creates a viable alternative to FPGAs, DSPs and ASICs suitable for deployment in high performance mobile applications.