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Title: Programmable architectures for the automated design of digital FIR filters using evolvable hardware
Author: Hounsell, Benjamin Iain
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2001
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Continuing increases in both the size and complexity of digital signal processing (DSP) systems places a considerable demand on the design engineer to develop hardware architectures capable of fulfilling the growing functional requirements expected of modern DSP devices. Automated circuit design techniques provide the design engineer with a tool to more effectively generate high performance signal processors capable of meeting demanding specifications. Evolvable hardware (EHW) is a relatively new approach to automated circuit design which utilises advances in reconfigurable hardware technology and the power of modern micro pro­cessors to generate circuits based on the principles of natural selection and evolution. This thesis investigates the suitability of software-biased and hardware oriented programmable platforms, configured via EHW, and tailored for the automated design of high performance DSP circuits. Performance criteria such as timing, area and circuit robustness are considered. A number of benchmarked DSP circuits were initially considered. It was shown that by using larger functional logic macros as building blocks EHW is more successful at generating circuit solutions than if only gate primitives are used. In addition, the circuits generated are of comparable or better performance than equivalent circuits developed using a standard digital design methodology. Results also indicated that for more complex DSP functions to be generated, EHW platforms must use larger functional blocks, constrained for a specific application. Finite Impulse Response (FIR) filters were identified as the backbone of many DSP applica­tions, and the multiplication unit was targeted as the performance critical component. A novel Programmable Arithmetic Logic Unit (PALU) was therefore developed as a functional building block suitable for automated digital filter design using EHW. The PALU replaces coefficient multiplication with a series of bit-shifts, additions and subtractions. Two distinct arrays of PALU were developed based on conventional FPGA and PLA re-configurable hardware architectures. Results show that a PLA architecture with 2 levels of hierarchical interconnect and column-based fixed tap outputs provides a platform most suited to automated filter design using the EHW technique. The PLA was also shown to be robust to faults covering up to 25% of the array when configured using EHW.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available