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Title: Low power techniques and architectures for multicarrier wireless receivers
Author: Hasan, Mohd.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2003
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Power consumption is a critical issue in portable wireless communication. Multicarrier code division multiple access (MC-CDMA) has a significant potential to be included as a standard in the next generation of mobile communication. This thesis investigates new low power architectures for a MC-CDMA receiver. The FFT processor is one of the major power consuming blocks in multicarrier systems based on Orthogonal frequency division multiplexing (OFDM), like MC-CDMA, wireless LANs etc. Three low power schemes are presented for reducing the power consumption in FFT processors namely the order based processing, the coefficient memory reduction and the simplified coefficient addressing. The order based processing scheme is based on a novel concept of using either the normal or two's complement form for only the real part of the coefficients selectively to minimise the Hamming distance between successive coefficients fed to the multipliers. This significantly reduces the switching activity at the coefficient input of the multiplier and hence the power consumption. The coefficient memory reduction scheme exploits the relationship among the coefficient values to reduce the coefficient memory size from N/2 locations to ((N/8)+l) locations for an N-point FFT, thereby saving both area and power for long FFTs. The proposed coefficient addressing scheme implements the complete coefficient addressing for all stages of a radix-2 FFT processor by using a simple multiplexer instead of a cascade of Barrel shifters. Low power single butterfly radix-2 FFT processor and radix-4 ordered pipelined FFT processor architectures based on the novel order based processing scheme are also proposed. The ordered low power radix-4 FFT processor is combined with the combiner to realise a low power MC-CDMA receiver. The power consumption in a MC-CDMA receiver can be further reduced by introducing the concept of dynamically altering the complexity of the receiver in real time as per the changing channel parameters such as the delay spread, maximum Doppler frequency, transmission rate and signal to noise ratio instead of using a receiver designed for the worst case scenario. The FFT size in multicarrier systems like MC-CDMA varies from 16-point to 1024-points depending upon the channel parameters. This thesis has proposed a reconfigurable 256-point FFT processor architecture that can be configured in real time to act as a 64-point or 16-point FFT processor to prove the concept. The power reduction is significant in moving from a fixed 256-point FFT to a reconfigurable 256-point FFT provided that the FFT size is varying over a large range, which is indeed, the case for a MC-CDMA receiver. This power reduction is achieved by using an appropriate FFT size (shorter FFTs) by disabling the clocks of the higher stages in real time. A reconfigurable pipelined MC-CDMA receiver architecture is also proposed that can be configured in real time to process 256 or 64 sub-carriers on the basis of the channel parameters. The power saving is obtained by disabling the first stage and the last ordering stage of the FFT processor and also by disabling the unused equaliser memory in the Combiner by switching from 256 to 64 sub-carriers. An FIR filter is also an important block in wireless receivers. A number of novel low power FIR filter cores based on different low power algorithms and their hybrid have also been presented.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available