Use this URL to cite or link to this record in EThOS:
Title: High level synthesis of memory architectures
Author: Fallside, Hamish
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1995
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
The development of high level tools for electronic design has been driven by the increasing demands of an ever more complex design process. The diversification in the use of electronic circuitry requires design tools tailored to application specific domains. Intelligent synthesis requires domain specific knowledge in addition to general synthesis techniques. The preponderance of synthesis systems in domains such as Digital Signal Processing is indicative of this need. Methods are presented here for the synthesis of memory architectures in one such domain: image processing. The research concentrates on performance synthesis. The techniques presented aim to optimise the design so as to minimise the memory access bottleneck of the eventual hardware implementation. The development of a synthesis system is described which serves to support the research. Algorithmic descriptions, coded in C, are processed by the tool in order to produce a structural description of a memory architecture able to implement the presented algorithms in hardware. Data flow and dependence analysis techniques are employed, these address the "high levelness" of the input algorithm, an important task if the designer is to be relieved of low level design detail. Methods for organising the algorithm's data in, and it's access from memory are presented, and experimental results are included. The organisation of data in memory is accomplished as part of the scheduling process for the user algorithm. The methods aim to optimise the hardware implementation by maximising the utilisation of the memory resources allocated during synthesis. In dealing with the access of data from memory, methods are presented for the automatic detection of memory inefficient structures in the user description, and their transformation into a representation yielding synthesised designs with greater memory throughput. Such designs are better able to support the user's algorithms within desired performance limitations. Examples are included which provide an evaluation of the techniques' efficacy.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available