Optimisation problems such as scheduling and resource allocation are hard, as large numbers of solutions exist for 'real' problems. Neural networks have been reported to find optimal solutions quickly. These networks derive their power from a massively parallel architecture, drawing its inspiration from the biological nervous system. There is a need for dedicated hardware implementations to accelerate neural computations. There is also a desire to develop autonomous neural systems. Digital circuits are tolerant of process variations. Digital circuits are however large. Analogue circuits are more compact and consume less power, but are dependent on the fabrication process for correct functionality. The choice between the two techniques is determined ultimately by the application. Analogue techniques are necessary to obtain a completely parallel implementation. Both the Hopfield/Tank and Kohonen networks used in optimisation rely upon matched circuit elements. Thus the development of process invariant analogue circuits for neural networks was the major aim of this thesis. Simulations are reported, of the Hopfield/Tank and the Kohonen networks, applied to the 10-city Travelling Salesman Problem (TSP). They confirm the reported optimisation abilities. The Kohonen network is shown to be faster and more robust than the Hopfield/Tank network. The results obtained from two fabricated devices are reported: a small scale test-chip and a large scale, generic building block device (EPSILON). These results show that the circuits developed in this thesis offer a significant immunity to the effects of process variations. The Kohonen network for the TSP was implemented on EPSILON. The Kohonen network was a very tough test for EPSILON, in that it requires a high degree of accuracy to be able to discriminate between the responses of neurons. Process variations prevented EPSILON from solving TSPs greater than 9 cities. The main conclusion of this thesis is that unless the neural algorithm actively compensates for the effects of process variations, the performance of a network implemented in an analogue VLSI is compromised.