Use this URL to cite or link to this record in EThOS:
Title: VLSI compatible parallel fabrication and characterisation of down-scaled multi-configuration silicon quantum dot devices
Author: Lin, Y. P.
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2014
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Electron spins in semiconductor quantum dots (QDs) have been increasingly shown in recent years to be a promising platform for realising the qubit – the basic unit of information in quantum computing. A crucial advantage of silicon QDs over alternative platforms is the potential for scalability in a quantum system to contain large numbers of qubits. Electron spins in Si-based QDs also have the benefit of a much longer spin coherence time relative to their extensively researched GaAs based counter parts – a prerequisite which gives the essential time needed for successful quantum gate operations and quantum computations. In this work, we propose and realise the first very large scale integration (VLSI) compatible process capable of fabricating scalable repeatable QD systems in parallel using silicon on insulator (SOI) technology. 3D finite element method (FEM) capacitance and single electron circuit simulations are first utilised to demonstrate the suitability of our double quantum dot (DQD) design dimensions in supporting single electron operation and detection. Here, we also present a new method of detection for single electron turnstile operations which makes use of the periodicity present in the charge stability diagram of a DQD. Through process optimisation, we fabricate 144 high density lithographically defined Si DQDs for the first time in parallel with 80% of the fabricated devices having dimensional variations of less than 5 nm. The novel use of hydrogen silsesquioxane (HSQ) resist with electron beam lithography (EBL) enabled the realisation of lithographically defined reproducible QD dimensions of an average of 51 nm with a standard deviation of 3.4 nm. Combined with an optimised thermal oxidation process, we demonstrate the precise fabrication of different QDs ranging from just 10.6 nm to over 20 nm. These are the smallest lithographically defined high density intrinsic SOI based QDs achieved to date. In addition, we demonstrate the flexibility of our fabrication process in its ability to realise a wide variety of complex device designs repeatedly. A key advantage of our process is its ability to support the scalable fabrication of QD devices without significantly affecting fabrication turnover time. Repeatable characteristic QD Coulomb oscillations and Coulomb diamonds signifying single electron tunnelling through our system are observed in electrical characteristics. Here we achieve precise independent simultaneous control of different QD’s single electron occupation as well as demonstrate evidence suggesting charge detection between QD channels. The unmatched level of clarity observed within Coulomb blockade diamond characteristics at 4.2K enables observations of line splitting of our QD’s excited states at this temperature, and readout of the spin orientation of sequential single electrons filling the QD. Through this spin readout, we gained an idea of the number of electrons stored on the QD and in turn, our ability to control the QD with precision down to the single electron limit. Statistically, we realise a parallel fabrication yield of 69% of devices demonstrating the ability to switch on and off repeatedly at 4K cryogenic temperatures with no leakage and sufficient channel resistances for single electron turnstile operations. This is the highest achieved yield observed to date for fabrication of intrinsic SOI based QD systems.
Supervisor: Mizuta, Hiroshi Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: QA75 Electronic computers. Computer science