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Title: A high-level methodology for VHDL-based synthesis
Author: Lim, Stephen E. L.
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 1992
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A language-based design methodology for the design of digital electronic circuits has been developed and implemented. The methodology is suitable for the high-level synthesis of Very Large Scale Integrated (VLSI) circuits, which are specified behaviourally in an IEEE standard hardware description language, VHDL. The output is a register-transfer level specification of the same circuit, with a bound hardware structure that meets the designer's area and speed requirements. We believe that this work is the first high-level synthesis research to preserve VHDL simulation semantics. To this end, we have developed a process model based on the VHDL process statement onto which all behavioural descriptions can be mapped. The synthesis methodology is based on two major sets of transformations: behavioural transformations and control/data flow graph (CDFG) transformations. The first employs several known language compiler optimisation techniques with a goal to minimising data path and controller area, or making user-directed tradeoffs between data path and controller area for an improved speed. CDFG transformations are the workhorse of data path and control synthesis. A graph notation and algebra are developed that support efficient algebraic graph transformations. Data path and control synthesis algorithms that operate on our CDFG model, the VHDL Intermediate Graph (VIG), are presented. Examples from the High-Level Synthesis Workshop benchmark suite are synthesised and results shown. To round up the work, several problems and issues that face high level synthesis both in research and in the real world are discussed in this thesis.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available