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Title: Tanlock PLL architectures with improved synchronization
Author: Anani, Nader
Awarding Body: Manchester Metropolitan University
Current Institution: Manchester Metropolitan University
Date of Award: 2013
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This thesis presents a number of digital phase-locked loop architectures, which are based on the Time Delay Digital Tanlock Loop (TDTL) system for improving various performance parameters of the original first- and second-order TDTL loops to alleviate some of their inherent limitations. These limitations include degradation of the linearity and span of the locking range in the first- and second-order loops respectively, and the acquisition speed of the first-order loop. The acquisition speed, the circuit complexity, the locking range and the noise performance of the original TDTL architecture were investigated and new improved architectures are proposed. The design, mathematical analysis, and testing results of the proposed architectures are presented. Evaluation using MATLAB/Simulink. of these architectures, under noisy and noise-free environments demonstrated significant improvements in the above performance parameters compared to the original TDTL system. Further, some of the proposed architectures are re-configurable which means that they can be optimized for a given performance parameter to match a given application requirement. In addition, in order to assess the real-time performance of these architectures, some were implemented using FPGA-based (field programmable gate array) development systems. Practical results obtained from those hardware modules concurred with the results obtained from simulation using MA TLAB/Simulink. Additionally, a number of new digital PLL system topologies for synchronizing a voltage source inverter with the low-voltage utility grid were developed and tested. The systems were tested, using MA TLAB/Simulink, under extreme conditions, such as introducing excessive total harmonic distortion (THD) in the grid voltage waveform. Despite the fact that such distortion can significantly falsify the zero-crossings, the proposed architectures were able to establish synchronization in less than 200 ms. In more realistic situations, locking was achieved within 100 ms. Such systems should find applications for interfacing renewable energy generating systems with the low-voltage utility grid.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available