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Title: Development of novel fabrication technology for SOI single electron transfer devices
Author: Alkhalil, Feras
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2013
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This report presents the design, simulation and fabrication of a spin qubit platform on ultrathin SOI (Silicon-on-Insulator) using A1 FinSET (Single electron transistor) gates and Si side gates. A new design layout is proposed for the double spin qubits co-integrated with a single electron electrometer, a waveguide and a nanomagnet. This platform aims to demonstrate the full operation of double spin qubits by integrating the following three key techniques in one compact footprint: a precisely controlled single electron transfer technology, a high speed charge detection technique and a single spin detection technology based on spin to charge conversion. A single electron transfer device (SETD) integrated with an electrometer is introduced here as the main building block of the spin qubit platform. The single electron transfer device consists of three nanowire (MOSETs) connected in series, and is capacitively coupled to an SET electrometer. A unique layout design for the SETD and a novel single electron transfer voltage pulse sequence are introduced. Simulation and dynamic analysis of this device operation are preformed using a finite element capacitance based simulation method and a Monte Carlo based single electron circuit simulation. The simulations demonstrated the ability of this platform to transfer single electrons and these characteristics are analyzed to optimize the layout. A novel fabrication process to realize high density silicon quantum dots (QDs) with A1 FinSET gates and close proximity Si gates on ultrathin SOI, for single electron transfer and detection, is successfully established with a number of different device layouts realized. In these devices, A1 FinSET gates surround an SOI nanowire channel forming electrically tunable potential barriers and defining QDs among them; Si plunger side gates are included to enable precise control of the QDs potential. Five SETD and electrometer device generations have been realized, tested and analyzed to improve the device yield; this extensive process development work is concluded with a novel fabrication approach to demonstrate successful FinSET A1 gae technology for SOI nanowires. This QDs platform is fabricated using a multi-layer electron beam lithography process that is fully compatible with metal oxide semiconductor technology. The fabrication process is fully developed with a yield of 92% and a great flexibility to enable the realization of more complex structures and even for devices beyond the scope of this project as shown in the appendices of this report.
Supervisor: Tsuchiya, Yoshishige Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering ; TS Manufactures