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Title: Design and simulation of planar electronic nanodevices for teraherz and memory applications
Author: Ali, Mubarak
Awarding Body: University of Manchester
Current Institution: University of Manchester
Date of Award: 2013
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The performances derived from current electronic technology are fast approaching a plateau since traditional vertically-layered devices are already in the scaling-limit range. The prospects of using planar devices as a solution have become increasingly promising. Besides, they provide additional advantages of being simple yet operating at very high speeds. In this study, the feasibility of utilising a planar nanoscale unipolar diode or a self-switching device (SSD) for terahertz emission and memory applications is demonstrated using simulations. Detailed characterisation of the devices is performed, paying close attention to their geometrical parameters and the surface-charge density which are crucial in planar electron transport.The emission from the SSD is profiled using electron dynamics in the device evidencing the presence of Gunn domains that lead to current oscillations. Following this, the device performance as determined by lithography-tuneable parameters of channel-length, channel-width and interface-charge density is investigated, in terms of their oscillating frequencies and current amplitudes. The study shows that the geometrical dimensions of the SSD can be tailored for optimum emission frequency and current oscillation magnitude, simply by altering the length and width of the channel, respectively. The highest fundamental frequency attained is 0.2 THz and higher harmonics could achieve up to 1 THz. Moreover, the interface-charge density has a much greater effect on the oscillation frequency than expected, providing some promise to extend emission frequency to a range that has been difficult to achieve using a solid-state device at room temperature.The flexibility of the SSD design has been further exploited to conceptualise a novel planar memory device aimed at overcoming the stagnated processing speeds of multilayer computational chips relying on interconnects. The structure is based on a high surface-to-volume ratio which enables conduction to be controlled by a memory storage region that can be charged and discharged by a control gate. Initially, structure dimensions are tuned and thereafter, the memory retention times resulting from the optimisation of geometrical and electrical parameters are discussed. The energy consumption of the device is much lower than flash memories, potentially useful for emerging low-power applications, particularly when device arrays are designed.
Supervisor: Song, Aimin Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Semiconductor ; Planar ; Nano ; Terahertz ; Memory ; Simulation ; Electronic ; Engineering