Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.579089
Title: Interconnect yield analysis and fault tolerance for field programmable gate arrays
Author: Campregher, Nicola
ISNI:       0000 0004 2743 4087
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2007
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Abstract:
In an effort to increase design flexibility and performance, FPGA manufacturers exploit the manufacturing process to its limits. This is particularly evident for the metal layers: latest technology allows up to 12 metal layers to be manufactured, and as a result the total area occupied by interconnects in an FPGA can be as high as 90% of the entire device. Following trends aiming to reduce wire widths and separations, the probability of a defect arising in the interconnect structures is significantly higher than anywhere else on the device, leading to high yield losses. The losses are particularly important for large FPGAs. Low yields of very large devices mean that the number of working dies out of whole wafer can be as low as one or two. Yields are very sensitive data: manufacturers are reluctant to provide any kind of information regarding their manufacturing process yield. This thesis presents a FPGA yield analysis framework to establish the extent of the yield loss problem. The developed models are based on well known yield analysis techniques, and provide a base for understanding and measuring yield losses, as well as estimating the potential benefits of yield enhancement techniques. The results show that yields of large devices manufactured with the latest technology process can be as low as 40% due to faults in the interconnect resources alone. Projections made using the SIA roadmap further show that future technology nodes will result in 0% yield for large devices. This thesis further proposes a new approach to interconnect fault tolerance in FPGAs. Firstly, a Built In Self Test procedure based on fault knowledge to locate faulty interconnect resources on the device is presented. Secondly, an innovative fault avoidance technique is presented: while previous approaches were based on hardware redundancy or reconfiguration, the technique presented exploits both the high regularity and the reconfiguration properties of FPGA devices. Based on fine grain redundancy, the scheme is demonstrated to improve wafer yields considerably while maintain timing and area degradation within acceptable limits. The fault tolerance technique is shown to provide yield enhancements of up to 90% while incurring in timing and area penalties of just 8.5% and 4.5% respectively.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.579089  DOI: Not available
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