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Title: Introducing a clocked muller C-element to increase logic throughput
Author: Howlett, Des Peter
ISNI:       0000 0004 2741 1635
Awarding Body: University of Reading
Current Institution: University of Reading
Date of Award: 2011
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Conventionally-designed digital circuits are encountering speed limits which cannot be overcome due to constraints imposed by the basic laws of physics. Synchronous designs are relatively easy to produce, but require the system clock to run at the speed of the slowest part of the entire circuit. Self-timed (asynchronous) circuits offer the promise of being able to use resources more effectively, however they require much more design effort while not always delivering the expected gains. This thesis presents a method of combining the advantages of both synchronous and asynchronous techniques by introducing and developing, for the first time, a clocked version of the well-known Muller C-Element as part of this research. Results of experiments demonstrating its effectiveness are given along with recommendations for further research and development.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available