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Title: Dynamic reconfiguration methods in FPGA-based softawre defined radio system for wireless mobile standards
Author: He, Ke
ISNI:       0000 0004 2743 7472
Awarding Body: University of Strathclyde
Current Institution: University of Strathclyde
Date of Award: 2012
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As wireless communication develops and evolves, the number of communication standards continues to increase. Therefore, the design of a Software Defined Radio (SDR) platform, which is aimed at supporting multiple standards and services for consumer applications with a high degree of flexibility, is of growing interest. SDR has been primarily associated with military applications to date. Field Programmable Gate Arrays (FPGAs) are programmable hardware devices which can perform complex calculations with high performance, and therefore, are well suited to wireless communication applications. FPGAs are selected as the reconfigurable devices used to perform various functionalities in the SDR system. However, although FPGAs are reconfigurable and thus can support standards and services switching in the SDR system, conventional SDR systems based on FPGAs can suffer from long reconfiguration overhead, high resource utilisation requirements, high power consumption, and inflexible standards switching. With the conversion from analogue to digital television, a large amount of licensed spectrum is being released, and this is often referred to as "TV white space". The propagation characteristics of these bands are capable of providing longer range and better indoor penetration for consumer compared to other operating frequencies in the Gigahertz range, thus are well suited to wireless communication. Therefore, it will be attractive to integrate TV white space functionality into SDR systems. In this thesis, an efficient design method for Digital Up Converter (DUC) architectures is proposed based on the existing DUC design methods in the Digital Front End (DFE) area. Furthermore, the proposed method can also be applied to TV white space DUC designs to enable the proposed SDR system to support more standards and modes. The novel physical layer architecture for SDR combines two dynamic reconfiguration technologies in supporting multiple standards, including 3rd Generation Partnership Project (3GPP) LTE, IEEE 802.16, IEEE 802.11, WCDMA and extensions to make compatible with white space. In addition, a study of power consumption relating to Partial Reconfiguration (PR) is undertaken based on implementation with the latest PR design flow. The proposed architecture is demonstrated to reduce FPGA reconfiguration overhead, resource utilisation and power consumption significantly, and to increase the degree of design flexibility, expansibility and reusability.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available