Use this URL to cite or link to this record in EThOS:
Title: Simulation of high fidelity control system designs using parallel architectures and floating point FPGA computing
Author: Apopei, Beniamin
ISNI:       0000 0004 2740 6983
Awarding Body: University of Sheffield
Current Institution: University of Sheffield
Date of Award: 2012
Availability of Full Text:
Access from EThOS:
Execution of Real Time simulation models is crucial in control systems but rarely achieved for highly complex feedback models. On the other hand, the use of Field Programmable Gate Arrays (FPGA) technology is proven to achieve execution speeds faster than real time for high fidelity models. However, as current FPGA applications are specialised and tool sets do not support basic control systems floating point blocks, significant effort is invested in order to incorporate new designs. These are typically non-intuitive, constructed and optimised manually. In order to overcome these difficulties, this thesis offers a standalone solution for simulation of control system designs using FPGAs. This is based on a floating point library of re-usable Hardware Descriptive Language (HDL) components, under System Generator toolbox, in Simulink. Also, extended research was performed in collaboration with Jaguar Land Rover, Rolls-Royce and Goodrich in order to underline general practices and main limitations of current methods found in Automotive and Aerospace Industries. The first contribution is a modelling design suite for floating point HDL control systems applications which reduces the design time to that of standard Simulink control systems simulation models. The most efficient FPGA design implementation is discussed. The presented methods are based on an extensive range of HDL design paths which assure the efficiency of the generated HDL structures, including comparisons not explored in the current literature. Contributions are offered for one of the major challenges found in generic FPGA implementations: the optimisation of the pipelining stages. A semi-automated throughput optimisation process was constructed on a rigorous mathematical model. Furthermore, the transition from serial to parallel architectures represents a considerable challenge due to an overwhelming number of unexplored options and conflicting factors. The work presented achieves the first reported complete parallelisation characterisation for generic MIMO L T1 state space systems using standalone FPGA implementations. This allows computational architectures to be split into most of the feasible combinations of serial and parallel FPGA computing blocks. Automatic optimisations of latency, occupied FPGA area and execution speed are attained and justified in respect to an increased number of possible implementations. These contributions are combined to offer a complete package for high fidelity control systems implementations. Results given by generic complex test case studies show a consistent execution time speed-up when compared to other industry based available technologies.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available