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Title: Topology emergence in networks-on-chip
Author: Jackson, Chris
Awarding Body: University of Bristol
Current Institution: University of Bristol
Date of Award: 2013
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We introduce a technique that allows the topology of a Network-on-Chip (NoC) to reconfigure continuously at runtime. Existing approaches have permitted reconfiguration between execu- tions of statically analysed applications. Starting from a regular mesh topology, our technique allows the network to adapt to a traffic pattern in order to reduce router activity and the average hop count of packets. We apply the concept of emergence so that macro-scale topology reconfig- , urations emerge as a consequence of repeatedly applying micro-scale rules at individual nodes. Our method utilises simple distributed single-hop message passing. This allows the technique to scale to arbitrary size networks with no extra logic cost or increased latency in reconfiguration. This is inspired by emergent goal-oriented networks, where global optimisations are produced by micro-scale reconfigurations. We believe that emergent processes are an efficient and scalable method of managing in- terconnect resources in large parallel systems. We present an architecture that reorganises the logical structure of the network as an example of the global optimisations that can be achieved using emergence. Each node of the network acts independently, applying a set of micro-rules that perform an analysis of local traffic to choose when to place or remove a local topology micro-reconfiguration known as a Skip-link. A set of placement rules limit the extent to which the topology may be deformed and are enforced by relaying topology changes to directly adjacent nodes, The bandwidth used by these communications is negligible. A new routing algorithm, Topology Adaptive Routing (TAR), is presented, In addition, asynchronous circuits to ensure packet ordering and synchronisation when placing a Skip-link are described, The system is evaluated using software simulation and a range of traffic types. Traditional permutation traffic is used to establish worst-case performance and a mono-fractal traffic synthesis model is used to generate traffic that resembles that of real applications. We compare the performance of a Skip-link enabled network with a standard mesh using Dimension Order Routing (DOR) and show that latency and energy reductions can be achieved over a static topology. The relationship between reduced average hop-count and critical load is investigated. In networks of up to 256 nodes, we achieve logical hop savings of up to 18% and critical load improvements of up to 33%. Per-flit energy savings of around 10% are also achieved. We also demonstrate that hop reductions increase with the size of the network.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available