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Title: Analysis and reduction of dc-link capacitor voltage/current stress in three-level PWM converters
Author: Orfanoudakis, G. I.
ISNI:       0000 0004 2734 4516
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2012
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Power electronic converters are in the heart of modern renewable energy and motor drive systems. This Thesis focuses on the converter dc-link capacitor (bank), which is a costly component and a common source of failures. The Thesis is divided into two parts. The first part examines the voltage and current stress induced on dc-link capacitors by the three most common converter topologies: The conventional two-level converter, the Neutral-Point-Clamped (NPC) three-level converter, and the Cascaded H-Bridge (CHB) three-level converter. The expressions derived for the rms capacitor current and its harmonics can be used as a tool for capacitor sizing. The harmonic analysis is then extended to systems that incorporate multiple converters connected to a common dc-link capacitor. The effect of introducing a phase shift to the converter carrier waveforms is examined, showing that reductions in the order of 30 to 50% in the common capacitor rms current can be achieved using appropriate phase shifts. The second part tackles the dc-link capacitor balancing problem, also known as Neutral Point (NP) balancing problem of the three-level NPC converter. Initially, a circuit that halves the voltage stress caused by the NP voltage oscillations (ripple) on the switching devices the NPC converter is proposed. The circuit consists of low voltage rated components which offer the advantages of lower losses, volume and cost, as compared to other balancing circuits. Subsequently, the study focuses on modulation strategies for the NPC converter. Starting with Nearest-Vector (NV) strategies, it proves that the criterion of the direction of dc-link capacitor imbalance, which is commonly adopted by NV strategies for performing the task of capacitor balancing, poses a barrier in achieving minimum NP voltage ripple. A new criterion is proposed instead, together with an algorithm that incorporates it into existing NV strategies. For the interesting case of NPC converters operating as motor drives, the resulting reduction in the amplitude of NP voltage ripple ranges from 30 to 50%. The study finishes with an extension of the previous concept to create hybrid (combinations of NV and non NV) strategies for the NPC converter. Hybrid strategies are proposed that can eliminate NP voltage ripple, introducing lower switching losses and output voltage distortion as compared to other methods used for the same purpose. The proposed strategies perform equally well when the converter operates with non linear or imbalanced loads. All results are verified by extensive simulations using MATLAB-Simulink.
Supervisor: Sharkh, Suleiman Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering