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Title: A FPGA based low-cost high speed QRD-RLS array processing
Author: Gao, Qiang
ISNI:       0000 0004 2740 0127
Awarding Body: University of Strathclyde
Current Institution: University of Strathclyde
Date of Award: 2012
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Over the last 30 years, Digital Signal Processing algorithm implementation has been driven by the continued progress and availability of high speed FPGA/ASIC circuit technology. The classic method of CORDIC (Coordinate Rotation DIgital Computer) arithmetic has been widely implemented as part of the computational requirements of the well known QR decomposition - Recursive Least Squares (RLS) algorithm. This thesis presents a novel FPGA implementation of a complex arithmetic valued QR decomposition which can function in adaptive filter applications and implement the adaptive filter weight extraction without using the traditional back-substitution method. In order to operate Givens rotation on a complex valued system, Double Angle Complex Rotation (DACR) is adopted to simplify the computational requirement of the classic Complex Givens Rotation (CGR). A new modified ‘processor-like’ architecture of a DACR based QR-RLS is presented. It features a single arithmetic Processing Element (PE) that has been extensively pipelined and efficiently shared for the implementation of the Givens transform associated with the QR algorithm. Annihilation-Reordering look-ahead Transformation (ART) was used to pipeline and hence speed up the real valued QR-RLS adaptive signal processing array without changing the filter’s convergence behavior. This thesis extends the ART technique to cope with a complex valued QR-RLS computation array, results in a novel Complex valued Annihilation-Reordering look-ahead Transformation (C-ART). The complex Givens rotation implemented in CORDIC arithmetic is suitable for the cut-set pipelining thus increasing the throughput.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available