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Title: The development of a novel all ternary InAlAs/InGaAs double heterojunction bipolar transistor (DHBT) for the design, simulation and fabrication of a static divide-by-2 frequency divider
Author: Knight, Robert John
ISNI:       0000 0004 2736 7961
Awarding Body: University of Manchester
Current Institution: University of Manchester
Date of Award: 2012
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The research focused on evaluating the feasibility into Microwave Monolithic Integrated Circuits (MMIC) fabrication capability, in the UK, using novel material type: all ternary In0.52Al0.48As/In0.53Ga0.47As lattice matched to InP substrate double heterojunction bipolar transistor (DHBT) technology; with the potential for providing high speed HBTs. The demonstration of a MMIC capability would follow with the development of a BiFET process that would satisfy SELEX Galileo circuit business needs. The research project complexity is divide into 5 phases: phase 1, the development of a high frequency In0.52Al0.48As / In0.53Ga0.47As lattice matched to InP substrate DHBT technology; phase 2, development of passive components; phase 3, the creation of two VBIC physical models; phase 4, the creation of a Process Development Kit (PDK) and phase 5, the design, simulation and fabrication of a divide-by-2 frequency divider using the technology developed in phase 1. Phase 1, concluded with a DHBT epitaxial design and fabrication that produced devices with a peak high frequency performance f_t = 140GHz and f_max = 95GHz at a current density Jc ≈ 1mA/µm2. This was achieved through the optimisation of the epitaxial design to reduce the base transit time τb through the introduction of a quasi electric field and thinning of base layer. To the best of the author’s knowledge, this is the highest f_t performance for a 1µm emitter width all ternary In0.52Al0.48As / In0.53Ga0.47As DHBT. The design, simulation and fabrication of a divide-by-2 frequency divider were only made possible by the successfully development of passive components (phase 2) and the VBIC model and PDK creation (phase 3 and 4). The divide-by-2 frequency divider design and simulation was done via the use of the PDK. The simulations resulted in a divide-by-2 frequency divider with a maximum operating frequency of 27GHz at a minimum input power of 2dBm. The fabrication of the MMIC resulted in a transistor component yield of 69%, which unfortunately resulted in a divide-by-2 frequency divider circuit yield of 0%. The fabrication of MMIC circuits is not possible with current state of the fabrication environment; however the only obstacle the University of Manchester (UoM) faces is low active component yield. To increase the active component yield to the 95% level required for high circuit yields, large capital investment into the fabrication equipment and human time into setting up the fabrication process to a repeatable and reliable standard is required.
Supervisor: Missous, Mohamed Sponsor: SELEX Galileo
Qualification Name: Thesis (Eng.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: DHBT ; InAlAs ; InGaAs ; Divide-by-2 Frequency Divider