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Title: Silicon thin films for mobile energy electronics
Author: Ahnood, A.
ISNI:       0000 0004 2730 2797
Awarding Body: University College London (University of London)
Current Institution: University College London (University of London)
Date of Award: 2011
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Consumer needs for mobile devices include the requirement for longer battery life, so that recharging can be performed less frequently or eliminated completely. To this end a key component of any mobile system is a high power and high energy density battery. An alternative to better batteries is for mobile devices to harvest some of their own energy. Solar energy is an accessible, free and environmentally friendly source of energy, making it ideal for powering mobile devices. In this work we present a low deposition temperature (150°C), thin-film solar power harvesting system. Low deposition temperature of thin film silicon and associated alloys allows for fabrication on plastic in order to realize lightweight and robust integrated systems. The system consists of a thin film transistor (TFT) circuit and thin film photovoltaic (PV) array. The circuit functions as a simple DC-DC regulator and maximum power point tracking unit (MPPT). Amorphous silicon (a-Si:H) is used as the primary thin-film material for the fabrication of the devices. One of the challenges when fabricating devices at low temperatures is the high defect density in a-Si:H due to hydrogen clustering. In here the He in addition to the SiH4 and H2 is used to minimise hydrogen clustering. Using the optimised films, TFT and PV devices are fabricated, and analysed. Low deposition temperatures influence TFT properties. Contact resistance and dynamic instability of TFTs are considered. New extraction methods and their effect on device mobility are presented. A power conditioning TFT circuit is proposed. A model is developed to analyse the circuit’s output stability as a function of stressing and light intensity. System efficiency and its dependence on circuit efficiency and solar cell utilisation are discussed. The PV array and the TFT circuit are fabricated using lithography techniques, with a maximum process temperature of 150°C. The circuit can provide a degree of output power stability over a wide range of light intensities and stressing times, making it suitable for use with SC. In this work peak system efficiency of 18% is achieved. Despite the circuit’s low efficiency, it has the advantage of fabrication on plastic substrates and better integrability within mobile devices.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available