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Title: Mapping of support vector machines on field programmable gate arrays
Author: Papadonikolakis, Markos
ISNI:       0000 0004 2728 5376
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2012
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Support Vector Machines (SVMs) are a powerful supervised learning method in the field of Machine Learning, which has drawn a lot of attention in the last two decades due to their high effectiveness and demonstrated prediction accuracy for a wide range of classification and regression tasks. Belonging to the class of supervised learning, this method comprises of two distinct phases, the SVM training and classification. When targeting large-scale problems, both SVM training and classification phases suffer from high execution times, due to their superlinear dependencies on the problem’s dimensionality and size. Therefore, that is an urgent need to accelerate these heavy load tasks, especially when the application imposes real-time constraints. The evolution and technology improvements on reconfigurable logic and, more specifically, the Field Programmable Gate Arrays (FPGAs) allow for the dedication of hardware resources to accelerate time consuming tasks. In the SVM case this is highly favorable, due to the potential for parallelization that the SVM training and classification tasks present. Moreover, many real-world classification problems present different and diverse precision and dynamic range requirements among their features. This is a strong motivation for the investigation and proposal of hardware-mapped architectures to accelerate the SVM training and classification. The FPGAs, due to their inherited custom-arithmetic potential and reconfigurability allow for the exploitation of this heterogeneity of different classification problems. This work focuses on the proposal of hardware-oriented architectures which can exploit the FPGA’s parallel processing potential, the reconfigurability and their custom precision-arithmetic in efficient ways, in order to accelerate the computational intensive tasks of SVM training and classification. The objective is to create highly scalable and adaptive FPGA architectures, which are able to maximize the utilized parallelization of the hardware resources, with respect to the problem’s characteristics and the application’s resource constraints. In this context, this work has proposed a heterogeneous FPGA architecture for the SVM training which allows for the exploitation of the targeted problem’s characteristics, such as the dimensionality and the precision requirements. The proposed architecture is a fully scalable solution, which maps the available FPGA resources in efficient ways, in order to increase parallelism and improve the SVM training performance. The scalability of the FPGA architecture is enhanced by the proposal of an algorithmic flow that balances the utilization of the heterogeneous resources allows for designing problem-specific circuits. This proposed FPGA architecture outperforms previous hardware-mapped approaches by more than 3 times in raw computational power. Further highlighting the achievements of this PhD work, this heterogeneous mapping idea is also exploited for the SVM classification, resulting in the proposal of the first cascade FPGA-based classifier, which exploits the FPGA reconfigurability in order to further improve the SVM classification time performance. For instance, this proposed architecture achieves in doubling the front-end system throughput of the SVM classification by a factor of 2 on a popular dataset, without introducing any resource utilization penalty.
Supervisor: Bouganis, Christos-Savvas Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral