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Title: Electromagnetic coupling in high frequency multilayer structures
Author: Cornock, Leigh
ISNI:       0000 0004 2727 2567
Awarding Body: University of Essex
Current Institution: University of Essex
Date of Award: 2012
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The interaction of the electromagnetic fields generated by electronic products, known as Electromagnetic Compatibility (EMC), is a significant consideration within the development process of all electronic products. As products get smaller, faster and more complex, the compliance with international EMC regulations becomes a growing issue. The design of multilayer printed circuit boards (PCS's) and integrated circuits (IC's) have a key impact on the EMC performance of a product and are at the forefront of this research. The PCS layout can be the cause of a product not meeting the required international EMC standards or even impeding the design from working due to the parasitic interaction of parts within the design. Understanding the interaction of elements within a PCS structure is critical to high speed designs. This research investigates the parasitic interaction of plated through holes, known as vias, within multilayer printed circuit board structures. Vias are an unavoidable element in the design of multilayer structures (either PCS or IC) but there is only limited research on the interaction between closely spaced vias. This research investigates how vias in multilayer structures interact. Explicitly this research presents: Unique frequency domain measurements and full wave models of the coupling between closely spaced via structures. A parametric investigation, using electromagnetic modelling, of the impact of via design and layout on the degree of coupling experienced between vias. Consequently design guides / rules of thumb on the reduction of coupling are generated. The development of a novel, lumped element equivalent circuit to enable: accurate and efficient simulation of the coupling between vias. This work helps progress theoretical understanding as well as the practical reality of laying out printed circuit boards. This adds to previous published work in the development of EMC design for high speed multilayer structures.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available