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Title: Fault response of inverter-based distributed generation
Author: Plet, Cornelis Arie
ISNI:       0000 0004 2718 3353
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2012
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The work presented in this thesis focuses on developing and experimentally verifying accurate analytical equivalent models of inverters during short-circuit conditions for use in numerical fault studies. In addition, a concept design for a variable speed generator that does not contribute to the local fault level is presented and verified by simulation and experiment. The flexibility of control offered by the application of power electronics in distribution networks is paramount in the transition to a decentralised power system but still faces significant technical challenges to widespread integration into the incumbent utility grid. Power electronic interfaces have historically only been used in rare cases and their effect on the network has hitherto often been ignored. The uptake of energy sources such as photovoltaics, variable speed wind, fuel cells, microturbines has caused a sufficient increase in grid connection requests for inverter interfaced generators, that before long their fault behaviour can no longer be neglected. The fault response of an inverter is dictated by its control strategy, its current limiting strategy and the reference frame in which they have been implemented. Current limiting typically breaks an inverter’s outer control loop and effectively turns it into a current source. Depending on the exact method of current limiting, linear analytical equivalent models have been developed whose source and impedance values can be expressed as a function of the inverters hardware parameters and controller gains evaluated at the fundamental frequency. The resulting models are compatible with conventional network analysis techniques and have been verified by comparing the results of such an analysis with experimental results. Fault models have been developed for stand-alone and grid-connected inverters. In congested networks the connection of an additional generator can cause the substation circuit breaker ratings to be exceeded. A full inverter interface can be controlled not to contribute to the fault current but is still prohibitively expensive at higher power levels. An alternative generator based on a doubly-fed induction generator is proposed and experimentally tested. By inserting a tap in the rotor winding, the voltage-per-turn can temporarily be increased to retain control of the quickly rising fault current without having to upgrade the machine-side inverter’s ratings. A fast thyristor-based tap changer inverter is proposed and experimentally verified that performs the pulse width modulation and diverts the modulated waveform to the desired tap on the rotor winding. The tap changer can be commutated in such a way as to achieve the fastest possible rate of current transfer during a tap change whilst avoiding voltage spikes by allowing any energy stored in the rotor leakage inductance to return to the DC-link. The developed fault models and zero fault current generator are a step towards familiarising utility engineers with power electronics and how they affect the operation of the distribution network. The availability of standardised models avoids the need for expensive and time-consuming time domain simulation based fault studies for inverter connection requests. The work presented in this thesis may act as a base for the development of standardised representations of power electronics in power networks.
Supervisor: Green, Tim Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral