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Title: Gated lateral silicon p-i-n junction photodiodes
Author: Abid, Kamran
ISNI:       0000 0004 2709 8255
Awarding Body: University of Glasgow
Current Institution: University of Glasgow
Date of Award: 2011
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Research in silicon photonics has recently seen a significant push to develop complete silicon-based optical components for optical communications. Silicon has shown its potential to overcome the bandwidth limitations of microprocessor interconnect, whereas, the silicon platform has already displayed the benefits of low manufacturing costs and CMOS compatibility. The work on “gated lateral silicon p-i-n junction photodiodes” has demonstrated the silicon potential, to detect optical radiations, compatibility to standard CMOS process flow and tuneable spectral response. The lateral structure of gated p-i-n junction photodiodes contributes to high responsivity to short wavelength radiations in these single and dual gate devices. The final objective of this work was to develop high responsivity, CMOS-compatible silicon photodiodes, where the spectral response can be modulated. The lateral p-i-n junction architecture led to high responsivity values, whereas, the MOS gate structure became the basis for tuneable spectral response. The MOS gate structure, made the devices appear as a transistor to the surrounding circuitry and the gate structure in dual gate devices can be used to modulate the spectral response of the device. Single gate devices showed higher responsivity values and comparatively high blue and ultraviolet (UV) response as compared to conventional photodiodes. Surface depletion region in these devices is utilized by placing a MOS gate structure and by patterning an integrated metal grating to detect polarized light. Single and dual gate devices with two variations were fabricated to characterise the device response. Novel lateral architecture of p-i-n junction photodiodes provides a surface depletion region. It is generally anticipated that photodetectors with surface depletion region might produce higher noise. In these devices the surface depletion region has a lateral continuation of gate dielectric which acts as a passivation layer and thus considerably reduced the noise. Physical device modelling studies were performed to verify the experimentally obtained results, which are provided in the relevant measurement chapters. In these devices the speed of operation is a compromise over the high responsivity, CMOS compatibility and tuneable spectral response.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: QC Physics ; TK Electrical engineering. Electronics Nuclear engineering