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Title: Biologically motivated circuits for third generation neural networks
Author: Dowrick, Thomas Martin
ISNI:       0000 0004 2707 6507
Awarding Body: University of Liverpool
Current Institution: University of Liverpool
Date of Award: 2011
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As interest in the possibilities of creating systems which can mimic the operation of biological nervous systems grows, small area, low power devices are required which can replicate the important features observed of neural cells. In addition, as advancements in CMOS technology become more challenging and expensive, alternative uses for existing silicon processing technologies and alternative computational paradigms are required, as indicated by the ITRS roadmap. In this thesis, three separate neural devices, capable of implementing the pertinent features of their biological counterparts, are described. The first is a compact silicon synapse, consisting of either two or three series connected MOSFETs, compatible with spike based communication methods. Plasticity is impleme`nted through an adjustable weight voltage, VW, which controls the amount of charge in the synapse. Short term depression and refraction are possible through a second control voltage, VP, which sets the rate at which the synaptic charge is replenished, with recovery times comparable to biology - between 0.5us and 10ms possible. With a transitor count of 3 and circuit area of 2.1µm x 6.2µm, the synapse is, to the author's knowledge, the most compact of any such device reported to date, while offering the same level of functionality. A neuron circuit, requiring three MOSFETs, is capable of summing excitatory and inhibitory synaptic inputs from the synapse cell, generating biologically plausible post synaptic potentials (PSPs). A MOSFET biased in subthreshold provides a method of adjusting the decay time of the PSP. The addition of a two stage CMOS inverter allows the neuron to generate spike outputs when the triggering voltage of the cell has been reached. A circuit for the implementation of an axonal delay, requiring only 5 transistors, is also described. Leakage through a subthreshold MOSFET creates a delay path between the output of a presynaptic neuron and the input of a post synaptic neuron, where delay times between 10s of milliseconds and 10s of nanoseconds are possible. Theoretical analysis, using parameters extracted from test MOS devices, is used to describe the operation of each device. Simulation results and results taken from fabricated chips confirm the validity of the approach. Methods by which the individual cells can be connected together to create larger scale networks are described, and a number of the issues associated with VLSI neural systems are considered.
Supervisor: Hall, Stephen Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral